微软公布 Clea Maia 300 推理 XPU 规格
微软在 Open Compute Project Summit 2026 上公布第三代自研推理加速器 Clea Maia 300 的规格,采用台积电 2 纳米 N2P 工艺和 chiplet 架构,封装内含 7 颗芯片与 8 个 HBM4 堆栈,配备 288 GB HBM4 和 18 TB/sec 内存带宽。微软称一机架 96 颗 Maia 300 的 token 吞吐量最高可达一机架 48 颗 Maia 200 的 7 倍,每瓦性能提升 2.5 倍,单机架功耗约 167 千瓦。该芯片面向更大规模的智能体推理负载,ATL 2.0 网络可将 128 个机架、12,288 颗加速器连入同一一致性域。
image. Like this: That is the biggest coherency domain we have heard of yet across the big cloud builders, and a heck of a lot larger than the 72 or 144 GPU coherency domains that Nvidia and AMD are doing in a coherent fashion across their rackscale systems, or even the 576 or 1,152 multi-tiered NVSwitch coherent fabrics that Nvidia is promising for production environments in the future. Google’s “Sunfish” TPU 8t training chip (which is not yet shipping) tops out at 9,600 TPUs in a coherency dom
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