DeepSeek V5 plans to pretrain on Ascend, as domestic AI chips enter a breakout year

DeepSeek Bets on Ascend: The Breakout Year for Domestic AI Chips Original source: Semiconductor Industry Observer Published: 2026-11-04 17:59 Author: Peng Cheng AI Chips DeepSeek Generate Poster When domestic GPUs outperform the H200, the story has only just begun.

As 2026 draws to a close, the narrative tone surrounding domestic AI chips has undergone a key shift. Over the past few years, the industry repeatedly asked "can it be used" and "do we dare to use it"; now, the question has become "is it worth using," and whether the next generation of large models dares to bet on it.

The change first occurred on the inference side, but the real critical watershed appeared on the training side. Positive signals emerged from both tracks almost simultaneously, pointing to the same judgment: domestic AI chips are no longer merely a substitute option under the shadow of sanctions; they are beginning to enter the core scenarios of first-tier computing demand.

01 Inference Side: From "It Runs" to "It Runs Better Than the H200"

Inference is the field where domestic chips first gained a firm foothold. Large model deployment has a relatively higher tolerance for ecosystem migration, and the fragmentation of inference scenarios has also left room for multiple tracks to advance in parallel. From 2022 to 2025, U.S. semiconductor export controls against China escalated layer by layer. In April 2025, the United States further tightened controls, forcing NVIDIA's H20 chip, specially customized for the Chinese market, to be discontinued, and the company consequently suffered approximately $4.5 billion in inventory losses and $8 billion in potential revenue losses. For the past three years, the H200 has been kept outside the Chinese market; and now, domestic AI chips have finally reached the specification level of the H200.

First is MetaX's Xiyun C600. This chip is equipped with 144GB of HBM3e memory, exceeding the 141GB specification of NVIDIA's H200. It officially entered mass production in May 2026 and was selected as "the first high-performance GPU built on a fully domestic supply chain," achieving a closed loop of the domestic supply chain across the entire chain from design to manufacturing, packaging, and then to the software stack. Surpassing the memory capacity by a single point is just a number on paper, but for the training and inference of today's leading large models, memory is the hard upper limit for accommodating model parameters and context. Crossing the 141GB line means that, for the first time, domestic GPUs are no longer in a position of still lagging behind on flagship-level hardware specifications.

After that came Iluvatar CoreX's Tiangai 300, released in July. The Tiangai 300 is based on the Tianshu architecture, equipped with a new generation of Tensor Core and Vector Core, provides stronger computing power, supports multiple precision formats such as FP4, FP8, BF16, and FP16, and also has 144GB of memory. Third-party actual testing showed that, under a typical prefill-decode disaggregated deployment, the Tiangai 300's converted single-card overall end-to-end throughput reached 1.05 times that of NVIDIA's H200; in a 64K long-context scenario, Attention performance was likewise 1.05 times that of the H200, multimodal generation inference throughput increased by about 2%–5%, and recommendation inference throughput in online businesses such as search, advertising, and recommendation increased by 21%. This is not a paper comparison of theoretical peak values, but a comparison of the actual output capability of the entire inference chain under specific models and deployment conditions. This is also the first general-purpose GPU in China whose measured performance reaches the level of the H200.

More new products surpassing the H200 are also being launched one after another. Biren Technology's next-generation GPU has recently been successfully brought up and is about to enter mass production. Sources say the new product is built on a domestic process and will outperform NVIDIA's H200. At the beginning of this year, Biren Technology had already clearly advanced the BR20X series based on a new-generation architecture. This series of chips natively supports a broader range of data formats such as FP8 and FP4, is equipped with larger memory and higher interconnect bandwidth, and aims to provide stronger computing power for cloud training and inference scenarios. After the BR20X, Biren also plans the BR30X for cloud training and inference.

Dongfang Suanxin will launch the DF2000 in Q4 this year, capable of reaching 15 TB/s memory access bandwidth and 1000TFLOPS@BF16, with performance parameters comprehensively surpassing NVIDIA's H200; in Q4 2027, it will launch the DF3000, capable of reaching 20 TB/s memory access bandwidth and 2000TFLOPS@BF16, doubling the improvement over the DF2000 and benchmarking against NVIDIA's B300.

The reason progress on the inference side has been faster is essentially that the commercial logic on this side has already completed a closed loop. IDC data shows that in the first half of 2026, NVIDIA's share of China's data center AI chip market fell to 34%, with shipments down 44% year on year; Huawei Ascend followed closely with a 28% share, narrowing the gap between the two to just 6 percentage points. Among the 11 Chinese chip companies tracked by IDC, 9 saw year-on-year shipment growth. Large-scale validation on the inference side has injected the industry with the scarcest thing: confidence.

02 Training Side: Domestic Chips Stand at the Door of Mainstream Large Model Pre-Training for the First Time

The overtaking on the inference side is quantitative change; the breakthrough on the training side is qualitative change.

On November 3, 2026, reports emerged that DeepSeek's next-generation large model, DeepSeek V5, is planned to be pre-trained on Ascend chips. Previously, Ascend's role in the DeepSeek system was limited to inference; V5 will be the first large model to natively rely on Ascend for training, with its core training compute pointing to Ascend 950 and the project timeline pointing to landing next year. The two sides had already completed a large amount of low-level operator adaptation and custom development during the V4 stage. For DeepSeek model-specific operators, Ascend had already begun custom optimization during the V4 stage, opening up the technical channel for full Ascend training in V5. In fact, as early as the end of September this year, DeepSeek open-sourced infrastructure components for the Ascend compute platform, covering the TileLang compilation tool, compute libraries, and distributed communication libraries, corresponding one-to-one with the previously open-sourced components for the NVIDIA platform. DeepSeek explicitly stated that every TileLang operator used in its training has a corresponding high-performance implementation on Ascend. This systematic alignment at the operator layer is the real engineering foundation for training migration. Without this step, V5's pre-training plan would be out of the question.

The loosening on the training side is not happening only at DeepSeek; in fact, there were signs long ago. In January 2026, Zhipu AI released GLM-Image, the first top-tier multimodal model to complete the entire training process entirely on Huawei Ascend chips, using Ascend Atlas 800T A2 devices and the MindSpore framework to complete a full closed loop from data preprocessing to large-scale training. On January 14, Zhipu, together with Huawei, open-sourced the model, and within 24 hours of open-sourcing it topped the Hugging Face Trending list of the global AI open-source community. This is also the first SOTA multimodal model to achieve full-process training relying on domestic chips.

Other domestic AI chips have also made breakthroughs on the training side. On January 13, Moore Threads and the Beijing Academy of Artificial Intelligence achieved a breakthrough: relying on the MTT S5000 thousand-card intelligent computing cluster and the FlagOS-Robo framework, they successfully completed full-process training of the BAAI self-developed embodied brain model RoboBrain 2.5. This result validated for the first time the usability and efficiency of domestic compute clusters in embodied intelligence large model training, marking that domestic AI infrastructure is now capable of handling complex multimodal tasks. In addition, combining a complete training suite with leading training optimization, reinforcement learning, and other technologies, the Kuae intelligent computing cluster built on Moore Threads' full-function GPUs has achieved breakthroughs in key dimensions. For example, in terms of high scalability, as cluster training scale continues to grow, it can maintain linear scaling efficiency of up to 95%; in terms of high precision, training precision is on par with mainstream international compute cards, and training loss curves are highly consistent; in terms of high stability, the cluster supports resumption of training from checkpoints, with effective training time accounting for more than 90%. On this basis, the Moore Threads Kuae intelligent computing cluster has completed a number of "domestic chips training domestic models" practical achievements, including complete training of the MoE-236B foundation model from scratch, and full-stack native training of Peking University's 5D world model EvoPhys-World, fully validating the full-link closed-loop capability of domestic chips in ultra-large-scale, ultra-long continuous and stable training.

Domestic chips on the training side are moving from marginal links such as post-training and fine-tuning toward the core link of mainstream large model pre-training, which had never truly been opened up before. Of course, the ecosystem migration cost on the training side remains the variable that determines the ceiling. Although the CANN software stack achieved full open-source opening in 2026, compatible with mainstream ecosystems such as PyTorch, vLLM, and TileLang, and MindSpore has also iterated to MXFP8 low-precision training support for Ascend 950, the developer inertia and operator richness accumulated by CUDA over more than a decade cannot be erased overnight. Whether V5's pre-training can run through as scheduled will be the first true "major test" for domestic training chips.

03 Behind the breakthroughs, it is not just isolated progress

If this counteroffensive is viewed only at the chip level, something more important will be missed. The reason these isolated breakthroughs can appear densely in the same time window is that the structural changes underneath are the real key.

The completeness of the industrial chain is visibly rising. An AI chip involves seven links from blueprint to landing: design, manufacturing, advanced packaging, equipment and materials, EDA, and storage. China has already formed considerable combat power in five links: chip design, mature and some advanced process foundry, advanced packaging, NAND flash memory, and DRAM memory. IP licensing, lithography machines, high-end EDA, and HBM remain weak points, but the nature of these weak points is changing from "completely blank" to "having a roadmap, a validation cycle, and a mass production timetable." Shenghe Jingwei has become the company with the largest 2.5D revenue scale in mainland China, with a market share of about 85%. In addition, Shenghe Jingwei is also continuously enriching and improving technology platforms such as 3D integration (3DIC) and 3D packaging, in order to achieve breakthroughs in more cutting-edge key technology areas of the integrated circuit manufacturing industry. ChangXin's global DRAM share climbed from 4% in the second quarter of 2025 to about 10% in the second quarter of 2026, and its fifth-generation DRAM platform achieved mass production. With the three foundations of manufacturing, packaging, and storage all moving upward at the same time, breakthroughs on the chip design side have a replicable landing point.

Supernodes have turned the "single-card gap" into a "system problem." When single-card process technology cannot catch up with TSMC and Nvidia in the short term, domestic computing power has chosen a more realistic path: using high-speed interconnect and system-level engineering to raise the effective computing power of multi-card clusters. The Ascend 384 supernode has already been deployed in more than 750 sets, and volume shipments of the 950DT supernode are targeted for the end of this year or early next year; Iluvatar CoreX's IXL144 enters training and high-concurrency inference scenarios with a density of 144 cards per rack and 10.1TB of memory. The maturity of supernodes means that the competitive unit for domestic chips has upgraded from "a single chip" to "a deliverable computing power system," which is the engineering prerequisite for the training side to take on large-model pre-training tasks.

Talent and capital are accelerating their concentration in the same direction. A few years ago, the predicament of domestic AI chips was largely a predicament of people: few people understood architecture, even fewer understood Chiplet and HBM advanced packaging, and composite roles capable of connecting hardware and the AI software stack were almost nowhere to be found. The current situation is that Enflame has offered annual packages of up to 1.8 million yuan to AI chip architects in the Chiplet/D2D direction, and "advanced packaging design engineer" and "chip packaging process engineer" have become standard options on the recruitment lists of Moore Threads and Cambricon. Although high-end talent in some fields is still scarce, the scarcity itself shows that demand genuinely exists and the industry is expanding, rather than being ignored. The capital side is equally active: Moffett AI completed nearly 2 billion yuan in financing within five months, Weina Hexin accumulated 3 billion yuan in financing within half a year, and Dongfang Suanxin's post-investment valuation after its A+ round exceeded 12.2 billion yuan. Money and people are flowing in the same direction, which is the most intuitive manifestation of the industry moving from an exploratory period into a construction period.

04 Conclusion

Looking together at the performance overtake on the inference side, the pre-training breakthrough on the training side, the vertical completion of the industrial chain, the system-level maturity of supernodes, and the accelerated convergence of talent and capital, this round of breakthroughs in domestic AI chips does not mean a victory of comprehensive leadership. The HBM gap remains obvious, the shortcomings in lithography machines and high-end EDA cannot be filled in two or three years, and the inertia of the CUDA ecosystem is far from dissipating. But domestic chips have already changed from a substitute that needed to be cared for and tolerated into a technical option that first-tier large-model companies can put into their core training roadmaps.

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