DeepSeek V5 plans to pretrain on Huawei Ascend 950 chips
According to reports, DeepSeek's next-generation large model, DeepSeek V5, plans to conduct pretraining on Huawei Ascend chips. Previously, Ascend chips were mainly used for inference tasks in DeepSeek large models; V5 will be its first large model to natively rely on Ascend 950 for training. The Ascend 950 series is divided into two models, 950PR and 950DT, both based on the third-generation Da Vinci architecture. The 950DT is equipped with 144GB of self-developed HBM and a memory access bandwidth of 4TB/s, while the 950PR is equipped with 128GB of on-chip memory and FP4 compute power reaching 1784 TFLOPS. People familiar with the matter said V5 plans to use Ascend 950 as its core training compute, with the project timeline pointing to launch next year.
Why read this
AI score 79
The report outlines the path of Ascend from the inference side to the pretraining side, so readers can judge the actual position of domestic compute in large-model training.
Topics
Body · AI translation
November 3 news: According to reports, DeepSeek's next-generation large model, DeepSeek V5, plans to conduct pre-training based on Huawei Ascend chips. Previously, Huawei Ascend chips were mainly used for inference tasks of DeepSeek large models; V5 will be its first large model to natively rely on Ascend 950 for training.
The Huawei Ascend 950 series is divided into two chips, 950PR and 950DT, both based on the third-generation Da Vinci architecture and mainly targeting training and inference scenarios for large models.
Among them, the 950DT is designed specifically for training and inference decode, equipped with 144GB of self-developed HBM, memory access bandwidth of 4TB/s, interconnect bandwidth of 2TB/s, and native support for low-precision formats such as FP8, MXFP8, and MXFP4, with MXFP4 compute power 4 times higher than the previous generation's BF16.
The 950PR focuses on the inference prefill stage, equipped with 128GB of on-chip memory, bandwidth of 1.6TB/s, and FP4 compute power reaching 1784 TFLOPS, emphasizing high throughput and cost control.
Looking back at the cooperation history between the two sides, the earliest large-scale deployment of DeepSeek on Ascend occurred around the 2025 Spring Festival. From New Year's Eve to the second day of the Lunar New Year, Huawei and DeepSeek completed the deployment and verification of more than 3,000 Ascend chips, successfully deploying the DeepSeek-V3/R1 large model to Huawei Cloud's Gui'an Data Center.
After the release of DeepSeek-V4 in April 2026, Huawei, through chip-model technology collaboration between the two sides, achieved full support across the entire Ascend SuperNode product series. DeepSeek disclosed at the time that, limited by high-end compute power, V4-Pro service throughput was limited, and it was expected that the Pro price would be significantly reduced after Ascend 950 SuperNodes go on sale in volume.
On September 30, DeepSeek further open-sourced infrastructure components for Ascend, covering the TileLang compilation tool, compute libraries, and communication libraries, corresponding one-to-one with NVIDIA platform open-source components, extending adaptation down to the infrastructure layer for training and inference.
Currently, the implementation of domestic compute power is mainly concentrated on the inference side, while the training side still needs improvement. Although a team previously completed full-parameter post-training of DeepSeek-V4-Pro relying on Ascend 910C, it has not yet involved basic pre-training.
If V5 completes pre-training based on Ascend, it will for the first time directly answer the core question of whether China's top large models can complete pre-training on domestic compute power.
According to people familiar with the matter, V5 plans to use Huawei Ascend 950 chips as its core training compute power, with the project timeline pointing to landing next year. If V5 successfully completes training based on Ascend 950, it will mark that domestic AI compute power has officially entered a new stage of supporting trillion-level large model pre-training.