NVIDIA Rubin Shipping Specs Adjusted: Memory Bandwidth Down 11%, External Network Up 12.5%

Futures promotion begin Futures promotion end Miaopai begin Miaopai end Video player start Video player end Market chart begin Market chart end

Source: Zhineng Auto article_adlist[

Produced by Zhineng Zhixin ]article_adlist

Oracle announced that Vera Rubin NVL72 has entered general availability on the OCI cloud platform, and Rubin has begun actually running business workloads for customers.

The shipping specifications that Nvidia quietly updated in September have been dug up: compute power and memory capacity are the same, both internal bandwidths have been lowered together, while the external network has instead been widened. Nearly a year after Rubin's release, the official numbers have consistently been marked as subject to change.

The new specifications apply to all Rubin hardware from the first day of shipment, with no transition period.

For a single Rubin GPU, NVFP4 inference compute is 50 PFLOPS and training is 35 PFLOPS, and the 288GB HBM4 consists of 8 stacks of 36GB each; none of this has changed.

What changed is this:

◎Memory bandwidth dropped from 22TB/s to 19.2TB/s, corresponding to a pin rate falling from 10.75Gbps to 9.375Gbps, a decrease of about 11%;

◎NVLink dropped from 3.6TB/s to 3.0TB/s, down 17%;

◎Bandwidth for the external network rose from 400GB/s to 450GB/s, up 12.5%.

Rack-level scaling is proportional:

◎NVL72's total memory bandwidth dropped from 1580TB/s to 1400TB/s,

◎NVLink dropped from 260TB/s to 216TB/s,

◎The external network rose from 28.8TB/s to 32.4TB/s, and the 20.7TB memory capacity remains unchanged.

The eight-card HGX NVL8 has the biggest differences:

◎Memory was cut from 2.3TB to 2.0TB, using only 7 of the 8 HBM4 stacks, leaving only about 250GB per card and about 16.8TB/s of bandwidth;

◎Total memory bandwidth fell from 176TB/s to 130TB/s, a drop of 26%, far more than NVL72's 11% decline;

◎NVLink dropped from 28.8TB/s to 24TB/s.

This applies to the x86 version, the Vera version, and all DGX systems based on NVL8.

Part 2

Why bandwidth changed first

HBM4 doubled the single-stack interface from 1024 bits to 2048 bits, with a JEDEC baseline rate of 8Gbps/pin.

◎Nvidia's originally planned 10.75Gbps far exceeded the standard, and even after dropping to 9.375Gbps it remains above the baseline;

◎Competitor AMD's MI455X runs at only 7.6Gbps.

English text is being prepared.

Why was the external network widened instead?

Model training spans thousands of GPUs, and inference distributes prefill, decoding, and caching across deployments, making cross-rack communication increasingly heavy.

The bottlenecks at the three layers of memory, interconnect, and network shift among one another as deployment scale grows. This adjustment is a system-level rebalancing, and for large-scale deployments with heavy cross-rack communication, it is actually beneficial.article_adlist[

Summary ]article_adlistarticle_adlist[

Nvidia's product specification adjustments are indeed dynamic. ]article_adlist

Special statement: The above content represents only the author's personal views or positions and does not represent the views or positions of Sina Finance Headlines. If you need to contact Sina Finance Headlines regarding the content, copyright, or other issues of the work, please do so within 30 days after the publication of the above content. news_keyword_pub,stock, iframe below body iframe below body General statement General statement QR code at end start QR code at end start

QR code at end start QR code at end start Editor name and work code Editor name and work code