SAIC and XHEART Join Forces to Bring 700 TOPS Large-Model Compute to Vehicles

SAIC Motor recently announced that it will collaborate with XHEART on model adaptation and vehicle application integration around a 700 TOPS large-model computing chip to drive improvements in intelligent driving experience. In the future, the two parties will also target large-model computing chips in the thousands-of-TOPS class, laying out plans for the next stage of autonomous driving requirements. At the same time, the two parties will also promote an upgrade of energy-efficiency evaluation standards: no longer looking only at paper metrics such as computing power per watt, but focusing more on response speed, system power consumption and sustained operational stability in actual driving tasks, so that the chip's computing capability can be translated into actual driving experience. According to the direction of cooperation between the two parties, the latency, power consumption and stability of complete driving tasks will become important evaluation criteria for model adaptation and vehicle application. With the development of end-to-end large models, VLA (vision-language-action models) and world models, intelligent driving systems need to process richer information, longer time sequences and more complex reasoning. The continuous improvement of model capabilities also places new demands on vehicle-side computing platforms: they must complete computations in a timely manner while satisfying constraints on power supply, heat dissipation, cost and long-term reliability. Against this background, SAIC Motor is working with ecosystem partners such as XHEART to advance collaboration in four directions—architecture, energy efficiency, process and computing power—bringing vehicle requirements earlier into model and chip design. Among these, changes in architecture design are particularly critical. In the past, vehicle-side models often had to adapt to existing chips; "large models defining chips" allows model structures, algorithms and data flows to participate earlier in chip architecture design. Capability goals are determined starting from driving tasks, then translated into the model's computing requirements, which are jointly realized by the chip and software. Around this approach, SAIC Motor is advancing operator fusion, parallel execution and task scheduling optimization to improve computing efficiency; optimizing the bus architecture and on-chip cache to ensure that critical computing tasks obtain sufficient data bandwidth. At the same time, it is making forward-looking arrangements for advanced memory technologies such as LPDDR6, and working with ecosystem partners such as XHEART to promote the mass-production application of 4-bit quantization in large-parameter intelligent driving models. Larger models being deployed in vehicles also require higher system energy efficiency. SAIC Motor and ecosystem partners such as XHEART will jointly optimize models, chips and vehicle heat dissipation, allocate computing power according to road-condition complexity, and reduce unnecessary energy consumption. The corresponding energy-efficiency evaluation standards will also be further upgraded: no longer looking only at paper metrics such as "TOPS/W" (how much computing power is provided per watt of power consumption), but examining actual performance in complete driving tasks, so that stronger driving capabilities can be delivered consistently across different vehicle models. Advanced processes need to be matched with mass-production conditions. SAIC Motor will evaluate technical solutions by combining chip design, packaging, heat dissipation, automotive-grade reliability and manufacturing costs, so that improvements in computing density and energy efficiency can be implemented in vehicle applications. The collaboration across architecture, energy efficiency and process creates the conditions for higher computing power to enter vehicles. At present, XHEART's latest chip, the X7 Ultra, reaches 700 TOPS of large-model computing power. The two parties will advance adaptation and application around this platform, and further explore large-model chips in the thousands-of-TOPS class. To meet the needs of different vehicle models, the two parties will also advance "same-origin architecture, multi-tier layout, full-scenario coverage," using the same underlying architecture to create products at different performance tiers, adapt to intelligent driving models of different scales, and provide computing solutions for the large-scale equipping of L3/L4 vehicle models.