Qualcomm Completes Preliminary Validation of HBC Stacked Memory, Dragonfly AI250 to Begin Sampling in First Half of Next Year
Qualcomm announced that it has completed preliminary validation of its High Bandwidth Compute (HBC) stacked memory architecture, which stacks multiple layers of DRAM on a small compute die for use in its Dragonfly data center AI accelerators. The testing used early samples with 2 layers of DRAM, while production products will have 4 layers; Qualcomm claims that its energy efficiency per unit of bandwidth per watt exceeds the HBM4 specification by 5 times, and that measured bandwidth is 18 times that of external LPDDR5X, but it did not disclose specific bandwidth figures. The first Dragonfly AI250 integrating HBC will begin sampling in the first half of next year, and Qualcomm also plans to use this technology in Snapdragon consumer products.
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